The present disclosure is generally related to electronic digital logic circuitry affecting signal sensitivity or transmission integrity and, more particularly, to a method and apparatus for variably controlling the propagation delay of a binary signal.
xe2x80x9cCMOSxe2x80x9d is an acronym for the Complementary Metal Oxide Semiconductor. As the name implies, CMOS devices are formed using metal conductors, oxide insulators, and xe2x80x9csemiconductors.xe2x80x9d Semiconductors are crystalline materials having electrical properties between that of a conductor and an insulator. The conductivity of semiconductor material can be precisely controlled in a process called xe2x80x9cdopingxe2x80x9d where a small amount of xe2x80x9cdopantxe2x80x9d is added to an otherwise pure, or xe2x80x9cintrinsic,xe2x80x9d semiconductor material. Doping leaves behind mobile, charged carriers for conducting electricity in the otherwise electrically-neutral semiconductor crystal lattice. When intrinsic semiconductor materials are doped so as to add negative charge carriers to the lattice, the material is referred to as an xe2x80x9cn-type,xe2x80x9d or donor xe2x80x9cextrinsicxe2x80x9d semiconductor, while the addition of positive carriers creates a xe2x80x9cp-type,xe2x80x9d acceptor material.
A xe2x80x9ctransistorxe2x80x9d is one particular type of semiconductor device that is noteworthy for its ability to operate as an electrical switch or amplifier, depending upon its configuration. There are two basic types of transistorsxe2x80x94bipolar (or junction) transistors and field-effect transistors (xe2x80x9cFETsxe2x80x9d). Although equivalent digital circuits can be created using either transistor technology, FET technology is often preferred and will be used for the various examples described here.
The term xe2x80x9cfield-effectxe2x80x9d is related to the application of an xe2x80x9celectromotive field,xe2x80x9d or voltage, to a xe2x80x9cgatexe2x80x9d terminal connected near the xe2x80x9cjunctionxe2x80x9d of the p-type and n-type materials. This gate voltage controls the size of a conductive xe2x80x9cchannelxe2x80x9d through which electrons must flow through as they pass from the xe2x80x9csourcexe2x80x9d terminal to the xe2x80x9cdrainxe2x80x9d terminal, or vice versa. Consequently, the gate voltage can be used to control the source-drain current through the channel in an FET.
Metal-oxide FETs, or xe2x80x9cMOSFETs,xe2x80x9d have an additional layer of a non-conductive oxide material (such as silicon dioxide) that insulates the gate terminal from the channel. Consequently, the gate current is very small regardless of the applied voltage so that circuits using MOSFETs can be made to consume, or xe2x80x9cdissipate,xe2x80x9d very little power. MOSFETs are characterized by their mode of operation and whether the channel is made from an n- or p-type semiconductor material. xe2x80x9cDepletion-modexe2x80x9d operation occurs when the gate-source voltage (between the gate and source terminals) is used to deplete the channel of free carriers so as to reduce the size of the conductive channel and increase its resistance. In contrast, xe2x80x9cenhancementmodexe2x80x9d operation occurs when the gate voltage is chosen to increase the size of the channel and thus decrease the source-drain resistance. Enhancement-mode MOSFETs are generally preferred, however, because the device will be normally xe2x80x9coffxe2x80x9d (i.e., the source drain resistance will be high) when the gate voltage falls below a certain xe2x80x9cthreshold value.xe2x80x9d
Nonetheless, even when the gate voltage is low enough to turn xe2x80x9coffxe2x80x9d an enhancement-mode MOSFET, the resistance between the source and drain terminals is still generally not large enough to prevent current from flowing between the source and drain under a large source-drain voltage. Consequently, as shown in FIG. 1, a MOSFET 5 is typically arranged in a digital circuit 10 with a resistor Rd, where G, D, S refer to the gate, source, and drain terminals. In addition, the source terminal is usually grounded in order to provide a reference voltage (of zero volts) with regard to the applied voltage at the drain Vdd.
In FIG. 1, the broken line inside the MOSFET 5 indicates that the transistor operates in enhancement mode and is therefore normally off (when Vin is zero). It will also be noted the source and substrate terminals are internally connected in the MOSFET symbol that is used in FIG. 1. However, depletion-mode and/or enhancement-mode MOSFETs with external and/or no connections between the source and substrate terminals may also be used. The direction of the arrow indicates whether the source and drain are connected by an n-type inversion layer as shown in FIG. 1, or a p-type inversion layer where the arrow is reversed. The MOSFET 5 is also equivalently represented with the circular xe2x80x9cenvelopexe2x80x9d removed.
In the circuit configuration shown in FIG. 1, the resistor Rd will act as a voltage divider when the transistor is conducting (and current is flowing between the source and drain) so as to prevent the transistor from receiving large currents. Consequently, when an input voltage Vin (that is larger than the threshold value) is applied to the gate terminal G, current will flow through Rd to create a corresponding low output voltage Vout near the gate terminal. Similarly, when input voltage Vin is removed, Vout will return to nearly the value of Vdd. For gate voltages that are between the threshold voltage and ground, the device will partially conduct, and thus act essentially as a variable resistor.
The direction of the source drain current will depend upon the polarity of the applied voltages as is well known in the art. However, since the output voltage Vout is opposite to the input voltage Vin, this simple digital circuit is called an xe2x80x9cinverter.xe2x80x9d Of course, xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d are relative terms that depend on the configuration of the applied voltages. Therefore, switching from any state to the another state is often more-generally referred to as xe2x80x9cactuatingxe2x80x9d from an xe2x80x9cassertedxe2x80x9d state to a xe2x80x9cdeassertedxe2x80x9d state.
The resistor Rd in FIG. 1 is referred to as a xe2x80x9cpassive loadxe2x80x9d because its power-consumption effect on the circuit does not change. FIG. 2 illustrates another inverter configuration 20 where the passive resistor Rd is replaced with another n-type enhancement MOSFET 5 that actuates, and thus provides full resistance, when Vdd is high. This second digital circuit configuration for an inverter shown in FIG. 2 is generally preferred because it is smaller and easier to fabricate than the one shown in FIG. 1.
FIG. 3 illustrates yet another embodiment of a conventional MOSFET inverter 30 including an (upper) p-type enhancement MOSFET 7 and a (lower) n-type enhancement MOSFET 5. The p-type enhancement-mode MOSFET 7 is xe2x80x9ccomplementaryxe2x80x9d to the n-type MOSFET 5 device in that all voltages and currents are reversed from the n-type device 5. Consequently, replacing one of the n-MOSFETS in the inverter 20 in FIG. 2 with a p-MOSFET creates a Complementary Metal-Oxide Semiconductor, or xe2x80x9cCMOS,xe2x80x9d inverter 30 where when one device is on, the other is off, and vice-versa. The basic CMOS inverter can be modified to build other complementary circuits as described below.
For example, the inputs and outputs of two of the CMOS inverters 30 shown in FIG. 3 can be connected in series to create the uni-directional xe2x80x9cdriverxe2x80x9d 40 shown in FIG. 4. The driver 40 is also referred to as a xe2x80x9cuni-directional CMOS transmission gate,xe2x80x9d or xe2x80x9cbuffer.xe2x80x9d Since there are two inverters in series, Vout in this device will follow Vin. However, due to the inherent xe2x80x9ccapacitance,xe2x80x9d or ability to store energy in the form of opposite charges (e.g., that are segregated in the different layers of material) in each of the transistors, each inverter 30 will require a small period of time before it fully changes the state of its charge. Thus, the inputs and outputs for several inverters 30 can be xe2x80x9ccascadedxe2x80x9d to create a delay between the time that Vout changes in response to Vin. Furthermore, increasing Vdd relative to ground will reduce this xe2x80x9csignal propagation delay,xe2x80x9d and vice versa. However, increasing Vdd also increases energy dissipation and reliability concerns due to increased oxide breakdowns, hot-electrons, and other effects that should be avoided. Signal propagation delay in cascaded CMOS inverters is further discussed in Rabey, xe2x80x9cDigital Integrated Circuits, A Design Perspective,xe2x80x9d chapter 5, galley sheets from http://bwrc.eecs.berkeley.edu/Classes/IcBook/NewChapters/ (Prentice Hall, 2d edition 2001) which is incorporated by reference here.
A signal propagation delay can also be created using a transmission gate, such as the bi-directional full CMOS transmission gate, or xe2x80x9cCMOS switch,xe2x80x9d 50 shown in FIG. 5. However, unlike the cascaded inverters 40 shown in FIG. 4, the bi-directional switch 50 will propagate a delayed voltage signal from Vin to Vout, and in the opposite direction, from Vout to Vin. CMOS digital circuits, transmission gates, and propagation delays are also discussed in more detail in Demassa et al., xe2x80x9cDigital Integrated Circuits,xe2x80x9d pp. 336-476 (John Wiley and Sons 1996) and which is also incorporated herein by reference.
Smith et al., xe2x80x9cCircuits Devices and Systems,xe2x80x9d pp. 212-215 (John Wiley and Sons 1976) generally describes how maximum power transfer occurs in an electrical circuit when the xe2x80x9cimpedancexe2x80x9d of the load matches the equivalent impedance of the power source, and is also incorporated by reference here. In simple terms, impedance can be thought of as the effective resistance of a circuit due to its ability to dissipate (through resistance) and store energy (through capacitance and/or inductance) at the same time. Impedance matching can then be analogized to an electrical power source having an inherent capacitance (or inductance) that starts to discharge its stored energy at the same time that a xe2x80x9cparasiticxe2x80x9d capacitance (or inductance) in the connected electrical device, or xe2x80x9cload,xe2x80x9d starts to recharge. If both of the capacitors (or inductors) have the same electrical properties, i.e. matched impedance, then they will transfer the same amount of xe2x80x9cenergyxe2x80x9d between each other, at roughly the same time, so as to minimize losses during these transfers of xe2x80x9creactive power.xe2x80x9d
In a similar manner, it can be shown that the propagation delay of signal from a voltage source that is connected to a digital circuit is minimized when the capacitance of the driver is matched to the inherent capacitance of the digital circuit to which it is connected. This phenomenon can be analogized to the inherent load capacitance (in the digital circuit) being able to charge and/or discharge (change state) more quickly when the inherent source capacitance (in the driver) discharges/charges with the same amount of energy at the same time. This propagation delay actually becomes longer as the voltage changes become more frequent and is, therefore, even more pronounced for faster digital circuits. Thus, proper impedance matching is very important, not only for providing adequate power, but also for ensuring that data signals propagate through digital circuits without unnecessary delay.
U.S. Pat. No. 5,581,197 to Motley et al., also incorporated by reference here, describes various undesirable side effects that follow from failing to match the output impedance of a driver to the characteristic impedance of a transmission line to which it is connected. It also states that variations in integrated circuit manufacturing processes and ambient operating temperature can combine to produce changes in the output driver stage impedance that must be compensated for. These, and other, variables affecting the operation of semiconductor devices are sometimes referred to as process (or photo), voltaic, temperature effects, or xe2x80x9cPVTxe2x80x9d effects. This patent goes on to disclose an apparatus having a programmable current source that determines a composite source impedance for the CMOS output driver stages that matches the load capacitance of a transmission line. However, Motley et al do not consider binary data signals or the problems associated with the propagation delay of those signals.
The power source for the Motley et al. device includes an operational amplifier, or xe2x80x9cop amp.xe2x80x9d An op amp is basically a xe2x80x9cdifferential amplifierxe2x80x9d that responds to a voltage difference between its positive and negative input terminals by producing a larger voltage at its output terminal that is in proportion to the differential input voltage. Op amps are generally characterized by their high xe2x80x9cgain,xe2x80x9d or ability to produce a large output voltage for a relatively small input differential voltage. Op amps are also characterized by their high input impedance and low output impedance. Consequently, they can be arranged in amplification circuits, such as the circuit 60 shown in FIG. 6, that draw little input current but can produce as much output current as is necessary in order to maintain an output voltage.
As shown in FIG. 6, the output voltage Vout of the amplification circuit 60 is equal to the inverse of the input voltage Vin multiplied by the resistance ratio Rvar/Rin. Thus the voltage gain between the input and output of the amplifier circuit 60 can be controlled by varying the resistance Rvar. Furthermore, since the gain of the amplifier circuit, Vout/Vin, is independent of (but less than) the gain xe2x80x9cAxe2x80x9d of the amplifier itself, the gain of the amplifier circuit is generally unaffected by temperature, input frequency, or device parameters associated with the electronic devices that form the op amp.
If Rvar is chosen to be equal to Rin in the amplification circuit of FIG. 6 the resulting amplification circuit has a gain of xe2x88x921 so that Vout will equal xe2x88x92Vin. Such amplification circuits are referred to as unity gain buffers, or xe2x80x9cvoltage followersxe2x80x9d since any change in voltage at the output caused by a change in load will cause the op amp to work harder (or less hard) in order to bring the output voltage back up (or down) to match the input voltage. In addition, since the input resistance of the op amp is typically very large relative to the load resistance, the op amp can provide substantial current while drawing nearly zero current from its power source. This isolation, or xe2x80x9cbuffering,xe2x80x9d of the load current from the source current produces a very stable output voltage regardless of changes in the load impedance. Op amps and amplifier circuits are also discussed in more detail in Smith, xe2x80x9cCircuits, Devices, and Systems,xe2x80x9d chapter 19 (John Wiley and Sons 1976) which is also incorporated by reference here.
Motley et al. also disclose that PVT compensation can be provided for by voltage follower circuits using the configuration shown in FIG. 7 where Rvar has been replaced with an n-type enhancement MOSFET 5 having its gate terminal connected to the amplifier output, its drain connected to ground, and its source connected to the non-inverting (+) amplifier input. Also, the inverting input to the op amp A is provided with a non-zero reference voltage. In this configuration, the MOSFET 5 acts essentially as a variable resister in order to slightly amplify, or attenuate, the voltage follower output Vout in response to PVT effects in the circuit being powered. More specifically, a higher Vout produces a lower resistance through MOSFET 5 so as to lower the feedback voltage, Vfb.
In addition, Motley et al. disclose the xe2x80x9cgate voltage mirrorxe2x80x9d 80 shown in FIG. 8. In essence, the gate voltage mirror 80 includes p-type MOSFET 7 and n-type MOSFET 5 connected in series so that they each have the same source-drain current. In addition, the gate of the p-type MOSFET is connected to its drain. In this configuration, as Vin on the n-type MOSFET gate (or xe2x80x9cVngatexe2x80x9d) goes higher, Vout on the p-type MOSFET gate (or xe2x80x9cVpgatexe2x80x9d) will go lower, so as to create a smaller voltage difference between Vngate and Vpgate, and vice versa.
The subject matter of U. S. Pat. Nos. 5,220,216 and 6,118,310, and European Pat. Application No. 868,026 A1 is also incorporated by reference here. U.S. Pat. No. 5,220,216 to Woo discloses CMOS gate having a programmable driving power characteristic for digitally varying its propagation delay. U.S. Pat. No. 6,118,310 to Esch discloses a digitally controlled output driver and method for impedance matching. EP 868 026 A1 to Watarai et al. discloses a variable delay CMOS circuit for reducing process dependence.
The present disclosure generally relates to an electronic circuit for processing a signal, and a signal processing method, including variable-delay propagation of a binary signal. For example, the circuit may include a transmission gate that receives a binary input signal and propagates a delayed binary output signal corresponding to the input signal.
The propagation delay is controlled by at least one control signal provided to the transmission gate. For example, the control signal may be provided by a voltage mirror in response to a non-binary input signal. The non-binary input signal may be set by a variable resistor and the device may include a voltage follower for maintaining the setting of the non-binary input signal. Furthermore, the voltage follower may include a gate-controlled feedback loop that compensates for PVT effects.
The variable-delay transmission gate preferably includes at least two inverters arranged in cascade, and a gate stacked on each side of the inverters. Each of the two stacked gates then controls a current through at least one of the inverters in response to complimentary control signals provided by the voltage mirror. For example, each of the attached gates may include at least one, but preferably two, field-effect transistors such as a complementary n- and p-type enhancement-mode MOSFETs.
Other features and advantages of the disclosed embodiments will also be apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all of these other systems, methods, features, and advantages be included within the scope of this description.